ECE241 — Digital Systems

Course discusses digital logic and introductory computer hardware. Design work is done in Verilog. Followed by ECE243 — Computer Organization.

We used the Fundamentals of Digital Logic with Verilog Design textbook by Stephen Brown and Zvonko Vranesic.

Concepts covered

Theory

• Moore’s law
• Number system
  • Binary number
  • Hexadecimal number
  • Signed number
  • Floating-point number
• Boolean algebra
  • De Morgan’s laws
• Function generation
  • Truth table
  • Karnaugh map
• Logic function expressions
  • Minterm and maxterm
  • SOP and POS form
  • Shannon’s expansion theorem
• Silicon cost
• Clock
  • Clock speed
  • Clock crossing
  • Metastability
• Reset
• Combinational circuit
• Sequential circuit
• FSMs
  • One-hot encoding
  • State minimisation
• Timing analysis

Circuits

• Logic gate
• Multiplexer
• Digital adder
  • Ripple carry adder
  • Carry lookahead adder
• Multiplier
• Arithmetic logic unit
• Latches
  • Latches
  • D-latch
• Flip-flop
  • Leader-follower flip-flop
  • T flip-flop
• Register
• Flip-flop applications
  • Counters
  • Rate divider
  • Arbiter
• Finite state machine
  • Datapath
  • Control path
• Memory
  • RAM
    • SRAM
    • DRAM
  • Memory block
  • Memory timing
  • Tri-state buffer
• Encoder
• Decoder
• Processor

Transistors

Transistor

• MOSFET
• CMOS
• Threshold voltage
• Transmission gate

Software

• PuTTY
• WinSCP
• Logisim
• Verilog
  • always block
  • case statement
  • Non-blocking assignment
• Quartus Prime
• ModelSim

Laboratory tools

• 7400-series ICs and breadboard
• Field-programmable gate array
  • Look-up table
• DE1-SoC
  • Common anode
  • Seven-segment display

Final project

• Clock crossing
• DE10-Lite
• VGA
• PS2 protocol

Submission

Lab work is submitted through the ECF computers. Some commands are:

• /cad2/ece241f/public/submit 7 part1.v part2.v to submit files, adjust as needed
• /cad2/ece241f/public/check_submission 7 to check if you actually submitted anything
• /cad2/ece241f/public/7/tester to run some test cases as a sanity check

The 24/7 FPGA lab is BA 3135.

Observations

Final project

160 in $x$-direction, 120 in $y$-direction 3-bit colour, only 8 different colours primitive version of VGA have 2D array in memory where each array element we have 3 bits frame buffer chunk of memory is current video frame

press on/off handler clock switch between keyboard and mouse every cycle

todo:

• help with audio
• help match nick’s output with eric’s fsm
• score fsm

Lab 5

We want a 4-bit counter from 0 to 15, displayed on HEX0. Active-high reset, up counter, counts at two clock speeds: 1 Hz for speed 0, and 0.5 Hz for speed 1. There’s a 50 MHz clock on the DE1-SoC.

We can’t change the clock speed to we work with what we have: we count the number of clock cycles. For example, for something to happen once every second, we count 50 million edges. Speed 0 counts $50\times 10^6$ edges. For speed 1, we count $100\times 10^6$ edges. Then how wide does the counter have to be? $2^{10}{2}^{10}{2}^7$ gets us about $128\times 10^6$, which is enough to count up to 100 million.

So we need a 27-but wide down counter for speed 1. Needs a parallel load (either 50 mil or 100 mil depending on the speed setting). This down counter is the enable for the 4-bit up counter.

The 4-bit up-counter receives the 50 MHz clock, but it only counts up only when there’s a proper output from the down counter.

And we need a synchronous reset attached to each. In rate divider we have a short implementation. We should check if enable should be 1 on reset or whether it should wait a full down cycle (then we use an assign statement at the end of the module).

For part 3 we have a morse code thing. The letter is selected by the switch. The short pulses are on for 0.5 seconds, the long for 1.5 seconds. When enable is turned on, then the LED should start. For example, B is -… then we can represent as 111010101, where we have 1 as 0.5 seconds on. This can be put into a shift register, left-most value — half a second is 25 million rising clock edges

we then just insert 0s. how to shift left? and insert 0s on the right? use the

reg [11:0] shiftReg;
// ..
shiftReg <= shiftReg << 1; // or
shiftReg <= {shiftReg[10:0], 1'b0};