ModelSim

ModelSim allows us to simulate logic circuits from Verilog code, and can be used in conjunction with Quartus Prime. Our simulations are written in .do scripting files, activatable from the command line. .do files are only for simple tests.

Why script? We need to prove that our design is working. Think about what the functionalities are, how we set the inputs, and what the expected outputs are.

ModelSim was discontinued and replaced with Questa.

Commands

Within the terminal:

• quit -sim turns off the simulation.
• do simul_file.do runs the simulation.

Within the .do files

New > Project, put all the files in. Eventually compile the files, select all the files, and Add Wave. Then we can use Clock to essentially generate a timing diagram.

The following commands are more or less the same for every project:

vlib work
 
vlog part2.v
 
vsim DisplayCounter
 
log {/*}
 
add wave {/*}

Respectively they:

• Set a working directory.
• Takes the given Verilog file as the working file.
• Takes the given module as the top-level module.
• Logs and adds the wave in the simulation.

Within the Verilog file, for the sake of the simulation, put in this line of code:

`timescale 1ns / 1ns // `timescale time_unit/time_precision

Then to force a clock signal, we can:

force {clock} 0,1 5 ns -r 20 ns

And for regular signals:

force {resetn} 1 // for a single bit value
force data_received 1111 // for a multi-bit value
run 40 ns

Reminders

• By default, ModelSim’s working directory is in the Intel FPGA folder. You should cd into the correct working directory.
• Occasionally also it’ll refuse to compile for an otherwise fine file. In cases like this, you may want to restart the simulator.
  • I also seem to get a few errors with setting vlib as part1 or something. Maybe it’s an issue with existing directories? But either way setting it as work seems to be fine.
• It’s not necessary to explicitly force signals on or off if they’re remaining constant from the cycle before.

Specific hardware

If generating specific hardware (like memory modules), additional parameters must be added.

vsim -L altera_mf_ver <module-name>