Creating a PS2 protocol interface for the DE1-SoC:
- SystemVerilog hardware interface
- C software interface with interrupts in Nios II
Software
Polling is usually not a great way to interface with IO devices. Modern operating systems use interrupts to handle IO events. This interface supports Nios interrupts.
Hardware
Successive layers of abstraction past the initial interface:
Reading/writing to signal > Controlling reading/writing > Interface to controller > FIFO that stores interface values
Testbenches are being written in coco-tb, a Python-based library for HDL testbenching. If this doesn’t work I may switch to a SystemVerilog-based testbencher. Barring something extraordinary I can go back to simple ModelSim scripts.
Should also add a FIFO. Circular FIFOs look good to me.