SystemVerilog

SystemVerilog is an HDL that is a superset of Verilog with additional features. This includes object-oriented features, the ability to specify testbenches, and more flexible syntax.¹

Language features

• Hierarchical design
• always block
• case statement
• Non-blocking assignment
• Universal Verification Methodology

Development environment

I use:

• VS Code as my text editor
• Metalware HDL Copilot as a linter

Resources

• IEEE Standard 1800-2017, which is the SystemVerilog specification
• ChipVerify
• SystemVerilog Tutorial by ASIC World
• LowRISC style guide
• SystemVerilog for Design, by Stuart Sutherland, Simon Davidmann, and Peter Flake

Footnotes

1. It is to Verilog what C++ is to C. ↩