SystemVerilog

SystemVerilog is an HDL that is a superset of Verilog with additional features. This includes object-oriented features, the ability to specify testbenches, and more flexible and expressive syntax.¹

Language features

• Hierarchical design
• always block (always_comb, always_ff)
• case statement
• Non-blocking assignment
• Universal Verification Methodology

Development environment

An opinionated set-up:

• Text editor — Visual Studio Code with extension Verilog/SystemVerilog Tools
• Testbenches and simulator — coco-tb with Questa (possibly iverilog too)
• Formatter and language server — Verible
• Linter — Slang

Resources

• General language resources
  • IEEE Standard 1800-2017, which is the SystemVerilog specification
  • LowRISC style guide
  • SystemVerilog Tutorial by ASIC World
• Digital verification
  • ChipVerify
  • SystemVerilog Assertions
• SystemVerilog for Design, by Stuart Sutherland, Simon Davidmann, and Peter Flake

Footnotes

1. It is to Verilog what C++ is to C. ↩