Design verification

Design verification is the process of ensuring the correctness of a design with respect to requirements and specification. This finds broad use in both software engineering and digital hardware engineering, but is especially important in the latter.

In digital hardware engineering, verification is an important step to comprehensively verify the HDL design is correct. This ensures that any bugs in the design don’t make it into a final chip (which can be expensive to rectify when too late in the cycle).

Approaches

Some broad types of verification approaches include:¹ As a list:

• Static verification
  • Code analysis
    • Linter
  • Formal methods
• Dynamic verification
  • Simulation
  • Prototyping
    • FPGAs

Sub-pages

• Approaches
  • Static verification
    • Code analysis (linters)
    • Formal methods
  • Dynamic verification
    • Simulation
    • Prototyping (FPGAs)
• Tools
  • Universal Verification Methodology (SystemVerilog)
  • coco-tb

Resources

• COMS30026 — Design Verification (University of Bristol, Kerstin Eder)
• Verification Guide

Footnotes

1. From Prof Kerstin Eder’s lecture slides from COMS30026 at the University of Bristol. ↩