Rate divider

A rate divider is a digital counter that takes a fast clock signal and outputs a slower pulse.

Implementation

module rateDivider(clock, reset, speed, enable);
	input clock, reset, speed;
	output reg enable;
	reg [26:0] downCount;
 
	always@(posedge clock)
	begin
		if (reset || downCount == 27'b0) begin
			enable = 'b1;
			if (!speed)
				downCount <= 27'd50000000;
			else
				downCount <= 27'd100000000;
		end
		else begin
			enable = 1'b0;
			downCount <= downCount - 1'b1;
		end
	end
endmodule

For the DE1-SoC, we have a 50 GHz clock. So the clock we input is the board’s clock.