Reset

In sequential circuits, we often have a reset element to help set initial values and reset the circuit back to a stable state. There’s a bit of confusing terminology:

• Low reset occurs when the value is 0. High reset is when the value is 1.
  • By convention, we name our reset signal ending with an n, i.e., resetn. The n denotes an active-low reset.
• Asynchronous reset is when the value of Q can be reset or pre-set at anytime, not only at the primary clock edge.
  • When we implement this in Verilog, we pass in either negedge or posedge of the reset, depending on the context of the circuit.
• Synchronous reset is aligned with the clock edge. In Verilog, we only pass in the primary clock edge in the sensitivity list and not the edge of the reset.