Clock skew

Clock skews are when the clock edge arrives at flip-flops at different times, like a clock delay. It’s used in digital systems design to avoid timing violations. Up to this point, we’ve been assuming the clock edge arrives at all the same time.

i.e., we have a delayed clock with the same frequency, just with a small phase shift, called $t_{\Delta }$

We essentially extend the deadline. By “launching” with one clock frequency, we’re able to “receive” a bit later with a lagged clock. So our new minimum period is:

$$t_{min}=t_{C{Q}_{max}}+t_{gate{s}_{max}}+t_{SU}-t_{\Delta }$$

which means we have a higher maximum clock frequency. To determine if we have any hold-time violations, we:

$$t_{max}=t_{C{Q}_{min}}+t_{gate{s}_{min}}\ge t_{hold}+t_{\Delta }$$

Addendums

What if we keep increasing the delay such that everything else is negligible and we get a huge clock frequency?¹ Hold time must be honoured, so we can’t just keep increasing. We have a bit of an available slack by determining the difference between $t_{max}$ and $t_{min}$.

Imagine though that we have a circuit attached to the output of the flip-flop — then we’ve also delayed that part of the circuit if we add a delay too, which limits how long we can add a delay.

How do we do a configurable delay? We use a tapped delay line. We can add two inverters in series, chain them together, attach their outputs to a mux and a select. Quartus Prime would ordinarily identify that it largely results in the same input and rip out the inverters, but we can add “don’t touch” comments to leave things in.

Footnotes

1. Prof Anderson says there’s no free lunch. ↩