The instructions for a processor tells the controller (FSM) what operation is to be executed. The instruction register holds the current instruction.
Instruction set architectures (ISAs) specify the capabilities of the processor, like what data types it supports or how many registers it has. Assembly language are human-readable instructions that approximate what a computer can do. They resemble the binary machine code (or instructions) that actually program it.
List
Most modern ISCs use a RISC-style architecture. CISC was prevalent prior to the 1970s.
Specification
An addressing scheme where we can access memory is a memory-to-memory architecture, with only control registers. All operands come directly from memory and are sent directly to memory. That said, because of the fetching and storing of results, this style takes many clock cycles to execute.
Register-to-register architecture (or load-store architecture) allows only one memory address for loading and storing of instructions. This is most common in modern processors; it requires a large amount of registers.
Immediate instructions allow instructions to be performed where one of the operands are constants not already contained in registers. The idea is it stores into one register temporarily for the computation. In general, we can’t do immediate operations with n-bit numbers on an n-bit system, because there needs to be sufficient space within the instruction encoding.
There are several broad classes of instructions:
- Branch instructions often rely on the
zregister. - Load/store instructions interface with memory.
Instruction encoding
The format of the instruction bits are divided into fields:
- The opcode field specifies the operation to be performed.
- The address field provides a memory address or an address that selects a processor register.
- The mode field specifies the way the address field is to be interpreted.
For instance, an add operation may contain the unique opcode for add, and the two registers it operates on.
Sequence
The idea with processors is that we pull data from memory into registers, perform the computations on the registers, and store results in memory. Take this instruction for the function using RISC-style execution:
- Load instruction from the program counter.
- Decode the instruction.
- Load in R2, content at address A
- Load in R3, content at address B
- Load into R4, contents of R2 + R3 from the ALU
- Store in address C, contents of R4
The specific operations take place on the datapath and the control to implement the function (i.e., the FSM) is handled with the control path.