RISC (reduced instruction set computers) refers to a broad type of instruction set architecture that restricts each instruction to fitting inside a single word of memory. Additionally, memory operations are done only via “load” or “store” instructions, and any operands needed must be in the processor’s registers.
The idea is that if each instruction occupies less space and all operands needed are already stored, then there can be higher performance. This comes at a cost of needing to use multiple instructions to specify complicated operations. Nowadays most ISCs use RISC-style architecture, with variations for their specific purpose. Complex instruction set computers have instructions that may span more than one word.
List
Instructions
As above, the idea with RISC is that:
- Each instruction fits in a single word.
- Memory operands are accessed only with “load” or “store” instructions.
- All operands used must be in the processor’s registers or given explicitly within the instruction word.
For instance, take the function . We need the following steps:
- Load in R2, content at address A
- Load in R3, content at address B
- Add into R4, contents of R2 + R3
- Store in address C, contents of R4
”Add” is a three-(operand/address) instruction:
Add — destination, source_1, source_2
”Store” is of the form:
Store — source, destination