A parallel port (PIT) device is used by computers to read and write input and output. Parallel ports send multiple bits of data at once, and computers may have multiple devices connected.
Oftentimes (especially in embedded systems), parallel ports have a special reserved address in memory, where writing/reading to that address interacts with the device. We call this memory-mapped IO.
We have two key mechanisms to interact with PIT devices: we either poll them (continuously check if finished) or we use interrupts (they tell us when they’re finished).
Interface
The Nios II processor has four registers in the PIT interface:
- +0 is the data register, DR.
- +4 is the direction register, DIR.
- +8 is the mask register, used to trigger interrupts.
- +12 is the edge register, used to capture transitions of 0 to 1 in an input.
The ways these are implemented will be specific to each IO device, i.e., the buttons on the DE1-SoC will handle things differently than the switches. Nevertheless, this behaviour remains the same:
- The edge register will flip a given bit for an event of interest. It must be reset by the programmer for further use, by writing a 1 into the register.
- Note that for the buttons on the DE1-SoC, the edge register will only flip once the press has been lifted.