In digital systems design, high-level synthesis (HLS) refers to the specification and design of logic circuit using a language like C, C++, SystemC, or MATLAB, instead of a lower-level hardware description language like Verilog or VHDL. The idea is that just as HDLs abstracted from working with gates and discrete chips, we can abstract further from HDLs with a higher-level language.
This is an active area of research.