RISC-V has very specific interrupt mechanisms.
Hardware-level
To facilitate interrupts, RISC-V processors have a few specialised registers:
- Supervisor exception program counter (SEPC): stores the address of the instruction that was in the middle of execution. This is a 64-bit register.
- Supervisor exception cause register (SCAUSE): indicates the reason for the interrupt. Also 64-bits, but most bits are unused (spec isn’t mature enough, I guess).
- This is sorted according to a priority listing if more than one exception occurs at a time.
The RISC-V implementation can vary where in the pipeline instructions should be interrupted. We could either: flush the instruction and restart it from the beginning after exception handling, or complete the instruction.