Outstanding questions
none at this time
Progress
2024-07-30
- Implementation properties — change some strategies
- Install FrontPanel software
- Use JTAG to download the bitstream
- Check if board is actually receiving inputs
- Modify pin assignments
- Roberto to find cable
- Study how they assign JTAG pins and change it on the board
- 4 things
- Fix any hold time violations by changing implementation strategy on Vivado
- Install OpalKelly FrontPanel software and try to download the bitstream to the board
- Study current pin assignments (intended for Genesys board) and adapt to OpalKelly board using the existing constraint file
- Checking the options for JTAG communication to the board
- JTAG may not be necessary
2024-07-29
- Bitstream has been built. Some notes:
- Vivado currently mentions possible hold time violations, due to bad/faulty connections.
- Also possible poor usage of resources: Vivado assumes certain ports are registers (perhaps not mapping RAM correctly?).
- Also rebuilt OpenOCD from source. Pulpissimo requires a custom version of OpenOCD since there’s a longstanding issue with the official RISC-V OpenOCD port.
2024-07-26
- Trying to compile any arbitrary bitstream (verifying it’s not a problem with the custom part I tried to input). So far none of the Digilent Nexys boards are compiling and neither is the Xilinx ZCU104.
- For Digilent boards, it doesn’t even launch Vivado. I suspect either a problem with the installed Vivado version (I’m unsure of this, since 2022.1 was a suggested version for the Digilent boards) or the files were not correctly installed.
- Looks like the latter — Vivado’s board manager doesn’t properly install and the files must be pulled from Digilent’s Git repository
- For the ZCU104, the compilation’s killed past a certain point. I believe this is due to insufficient RAM memory.
- This fix was to create an extra swap memory partition, which Vivado relies on.
- For Digilent boards, it doesn’t even launch Vivado. I suspect either a problem with the installed Vivado version (I’m unsure of this, since 2022.1 was a suggested version for the Digilent boards) or the files were not correctly installed.
- Replicated a new build process for the OpalKelly ZEM7310.
2024-07-25
- Mustafa is away with COVID and is unable to hand over the Arty Z7.
- In lieu of this, Roberto suggested attempting to build a bitstream for the Opal Kelly XEM7310 (with a Xilinx Artix-7)
- I’ve been having space issues with the Vivado installation — 2022.1 requires 150 GB free and my Linux machine only had ~30 GB free
- I’ve since wiped the Windows 11 install on my Linux machine and repartitioned it as a Linux filesystem drive
- Installed Vivado on a newly partitioned drive
- So far running into problems relating to dependencies — Vivado is telling me that the specific board part isn’t found, even if it’s definitely installed (and verifiable with the
get_board_parts
Tcl command)
2024-07-24
- Mustafa has a Digilent Arty Z7 but this is unverified to work and missing a power supply cable
- Spent today running regression tests and familiarising myself with the codebase more
2024-07-23
- Currently running regression tests — previous script that automated each test is no longer available
- Most tests working, exceptions include: machine learning tests, I2C
- Meeting notes
- Progress — simple runtime working with Questa, most tests are working with some exceptions
- Outstanding questions
- If I run into problems with Questa, I’d need to ask the professor to create a user for me on the ECE (graduate?) machines and give access to a license
- Re: communication, a weekly sync meeting looks like the best option. I can reach out to Roberto via Discord if I run into any problems
- Previous PULP work
- SDK was previously not explored, since the simple runtime required a significant amount of set-up/fix work from the previous student. Once the simple runtime was working, they went straight to the FPGA implementation
- Pulpissimo was taped out, not the full PULP SoC or just the smaller RI5CY core
- Main purpose of Pulpissimo was to do “mask generation” for one of the image sensor group’s projects — there were three main platforms taped out: 2 mask accelerators that were custom designed, and a RISC-V microcontroller that would generate arbitrary masks
- The mask accelerators were debugged, but not the RISC-V core. This is probably going to be my responsibility
- Next steps
- Can start working with FPGA board, Genesys 2, Nexys 2, Nexys Video; to contact Mustafa to get a board
- To learn how to use OpenOCD to program the board with JTAG and figure out a communication system between the FPGA and ASIC
- If there’s remaining time and/or interest, we can think about possible custom modifications (not specific)
2024-07-22
- https://www.youtube.com/watch?v=B7BtaYh3VqI — video from PULP describing the Pulpissimo architecture
2024-07-19
- Runtime is now working with hello world example in Questa — some notes
- Simple runtime works as promised in the repository
- SDK is not working whatsoever — I’ve tried around 5 different build methods and the C++ requires a few dozen hotfixes at compile-time. Python incompatibilities as well within the code
- Python 3.{11, 12} breaks the runtime build — this requires a small hotfix with the string
'rU'
to just'r'
- We’re running the most recent version of Pulpissimo and the GNU toolchain — there are likely material changes and fixes from when the previous student was using this in 2022
- Shell commands above for best reproducibility
2024-07-18
- Recompiling RISC-V GNU toolchain: two main problems I’m facing with recommended build settings
- Original path settings don’t properly compile binary files
- Changing this to a less permissive directory fixes a problem with a missing GCC binary
- Architecture settings do not actually build for Pulp, but instead a generic arch
- Now running into a new problem with a “broken assembler”. Root problem seems to be again GNU toolchain and custom Pulp instructions. Requires a recompile (3-4 hours).
- Looks like a problem with the GNU toolchain itself — Pulp has two versions (https://github.com/pulp-platform/riscv-gnu-toolchain most recent; https://github.com/pulp-platform/pulp-riscv-gnu-toolchain older). Previous users were able to get the second link working. First link’s install results in a broken build.
- Original path settings don’t properly compile binary files
- Potentially going to run into problems with Questa. Currently running on Questa Intel FPGA Starter Version — so far Pulpissimo has been able to build with Questa but:
- Performance issues compared to full edition of Questa
- Potential to stall due to unsupported simulation settings between full/starter versions of Questa
- Resolved by getting a full license of ModelSim/Questa — past student worked with lab computers for this
2024-07-17
- Software installations, Git repository cloning
- Able to build Pulpissimo with Questa
- Path problems with Questa, toolchain — later resolved