A Makefile specifies instructions for how software programs should be compiled — it specifies all the dependencies and how the different files should be linked and compiled. It relies on a Unix utility called make that checks the time a file was last modified and what exactly needs to be recompiled.
Basics
Makefiles consist of a set of rules (or targets). A rule generally looks like:
targets: prerequisites
command
command
command- Targets refer to a specific Make command. When we type
make <TARGET>, it runs the commands in the rule. - Commands are done with operating system utilities (basically anything we’d run in the shell). They must be preceded with a
<TAB>. - Pre-requisites are targets that need to be run before any commands in the rule.
- Note that this can also include object files (
.o).makewill interpret this as compiling the object file before subsequent commands, which is helpful for specifying compilation dependencies for re-compilation upon changes.
- Note that this can also include object files (
The -jn flag will parallelise compilation, where n is a value that specifies how many build steps should be executed in parallel. Common values for n include 4 or 8, i.e., make -j8. We can also compile up to the number of cores in our CPU.
Resources
- Learn Makefile, by Chase Lambert
- GNU Introduction to Makefiles