One problem in processor pipeline design occurs with branch instructions. In this case, we run into the problem where we may only execute an instruction conditionally. The naïve approach is to wait for the branch instruction to finish, but this takes an extra clock cycle. Branch prediction techniques try to predict instruction execution, with some branches taken and some as untaken.
Dynamic prediction
Dynamic approaches try to predict branch execution during runtime by looking up the address of the instruction to see if the the conditional branch was taken the last time the instruction was executed. This is done via a branch prediction buffer (or branch history), which is a small piece of memory that contains a bit indicating whether the branch was recently taken.
A 1-bit buffer is a pretty naïve approach. We basically run into the same problem as direct cache mapping, where it’s probably from a different conditional branch.
Even though this is a simple approach, it does eliminate the amount of times we need to flush out the datapath pipeline registers. Increasing the number of bits can also help remedy this.